Reduction of the surface roughness of Geon-insulator layers up to sub-nanometer range by chemical mechanical polishing

4088 | P a g e c o u n c i l f o r I n n o v a t i v e R e s e a r c h J u n e 2 0 1 6 w w w . c i r w o r l d . c o m Reduction of the surface roughness of Ge-on-insulator layers up to subnanometer range by chemical mechanical polishing V. Manimuthu, M. Arivanandhan, Y. Hayakawa and H. Ikeda †Department of Nanovision Technology, Shizuoka University, Shizuoka, Hamamatsu 432-8011, Japan ‡Research Institute of Electronics, Shizuoka University, Shizuoka, Hamamatsu 432-8011, Japan manimuthu@rie.shizuoka.ac.jp arivucz@gmail.com royhaya@ipc.shizuoka.ac.jp ikeda.hiroya@shizuoka.ac.jp ABSTRACT


INTRODUCTION
Nanostructured Ge and SiGe have attracted considerable attention for use in thermoelectric power generators to achieve a higher efficiency than that of Si devices I-IV .To fabricate Ge and SiGe nanostructures by photolithography, ultra-thin Geand SiGe-on-insulator (GOI and SGOI) substrates with extremely low surface roughness are required V .Despite tremendous efforts made by researchers, preparation of ultra-thin GOI and SGOI substrates with sub-nanometer surface roughness remains a challenging task VI,VII .Moreover, there are several issues to be resolved regarding the properties of ultra-thin GOI and SGOI substrates.One of the issues that arise during the fabrication process, such as direct waferbonding is surface roughening during annealing, which usually performed to further enhance the bonding strength of GOI and the other is crystallinity degradation in the GOI and SGOI layers.From the viewpoint of size effect in nanostructures, surface roughness degrades the quantum effect owing to the fluctuation in quantized energy states.The electronic properties of the nanostructured Ge and SiGe are also degraded by the increase in carrier scattering resulting from the higher surface roughness and defect formation.Hence, the surface roughness must be reduced up to the sub-nanometer range.
In the current state of the art of Si-based electronic devices, the minimum feature size is now less than 10 nm in dimension.This is possible because the electronic device grade of Si surface roughness is below 0.2 nm VIII,IX , which can be achieved through chemical mechanical polishing (CMP).However, in the case of Ge, it is too difficult to achieve such a low surface roughness on a direct wafer-bonded GOI surface without damaging the interfaces of the device.Moreover, a series of annealing and pressing process must be performed and a thin intentionally grown thermal oxide layer is needed to reduce the surface/sidewall roughness of the GOI X-XII .Therefore, reducing the surface roughness of a direct waferbonded GOI substrate remains a challenging matter.
In this paper, we describe the investigation of two different thinning processes, used to obtain GOI layers with minimal surface roughness.The root-mean-square (RMS) roughness values of direct wafer-bonded GOI surfaces thinned by either CMP or wet chemical etching (WCE) were comparatively analyzed in pursuit of an extremely flat GOI surface with subnanometer roughness for the fabrication of Ge nanostructures.Moreover, the obtained RMS roughness was relatively low compared to previously reported values.

EXPERIMENTAL METHODS
A 300-µm-thick p-type Ge(100) wafer and a 370-µm-thick thermally-oxidized p-type Si wafer with an oxide thickness of 100 nm were used for the fabrication of a GOI substrate by direct wafer-bonding.After bonding, the GOI substrate was subjected to a thermal annealing treatment at 400 °C in an N2 atmosphere for 1 h to further strengthen the bonding at the Ge/SiO2.Subsequently, thinning was performed by mechanical polishing with slurry containing diamond particles XIII , to reduce the GOI layer thickness to below 5 µm.The samples were then divided into two groups.The first group was polished by mechanical polishing (MP) combined with CMP using colloidal silica (Glanzox 3000) with the polishing rate of 10 µm/min.The second group was polished by mechanical polishing combined with WCE in an H3PO4:H2O2:H2O solution, at an etch rate of 130 nm/min XIV .The CMP and WCE thinning processes of GOI layer were performed in the room temperature at around 24 °C.The thinning process tools for MP combined with CMP and WCE were shown in Figures 1(a  and 1(b).Table .1 shows the thinning process conditions for obtaining sub-nanometer surface roughness in direct waferbonded GOI layers.
The surface morphology of the thinned GOI layers was observed by dynamic force microscopy (DFM), with scanned areas of 2 µm х 2 µm and 10 µm х 10 µm.RMS roughness values were determined from the DFM images.The GOI layer thickness and the quality of the Ge/SiO2 interface were characterized by scanning electron microscopy (SEM).Optical microscopy was used to observe the formation of etch pits and hillocks on the GOI surface over a larger area.In order to observe defect formation over a larger area, the surfaces of as-bonded and thinned GOI layers were investigated.In the WCE process, the etching solutions are usually sensitive to the local stress level, so the etch rate of the perfect crystal lattice differs from the etch rate at defect sites XV .This anisotropic etching creates etch pits or hillocks, which can be identified and counted using a digital optical microscope.Figures 4(a), 4(b) and 4(c) show optical photographs of the surfaces of as-bonded and CMP-thinned GOI layers.The figures clearly show that no development of etch pits was observed after mechanical polishing combined with CMP.However, etch artifacts were identified on the surface of the GOI layer after WCE processing.The irregular square-shaped defects shown in Figures. 4(d) and 4(e) are clearly ascribed to etch artifacts.They do not all have the same crystal defect because their shapes, sizes and edges differ from those of a regular etch pit pattern and their orientation is non-crystallographic in nature.Furthermore, the squares were too large to be related to crystal defects.Therefore, the formation of the etch artifacts was not related to crystal defects nor was it an anisotropic etching effect.The etch artifacts are probably due to the chemical precipitation of excess phosphorus ions present from the etching solutions.
As a result, a very smooth device grade GOI layer can be achieved through CMP rather than WCE.Therefore, we believe that, GOI layer thinned by CMP process is essential for the enhancement in the electronic properties of future nanostructured Ge-based thermoelectric devices.

SUMMARY
We fabricated a p-type GOI layer using a direct wafer-bonding technique and confirmed that the GOI surface was rough after the annealing process.We analyzed the influence of the layer thinning process on the surface roughness of the GOI layer and obtained a device grade GOI surface with an RMS roughness of ~0.3 nm by mechanical polishing combined with CMP.Furthermore, optical and SEM images showed a high interface and crystal quality in the CMP-thinned GOI substrates, which should make them suitable for the fabrication of ultra-thin GOI surfaces through direct wafer-bonding for future advanced Ge and SiGe nanostructures.
u m e 1 1 N u m b e r 1 0 J o u r n a l o f A d v a n c e s i n P h y s i c s 4089 | P a g e c o u n c i l f o r I n n o v a t i v e R e s e a r c h J une 2016 w w w .c i r w o r l d .c o m

Fig 1 :Fig 2 :
Fig 1: Thinning process tools (a) MP combined with CMP and (b) MP combined with WCE.