Influence of annealing temperature on the electrical, structural and surface morphology properties of Au/Cr Schottky contacts on n-type InP

The influence of rapid thermal annealing on the electrical and structural properties of Au/Cr/n-InP Schottky diode have been investigated by the current-voltage (I-V), capacitance-voltage (C-V), auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The Schottky barrier height (SBH) and ideality factor (n) of the as-deposited Au/Cr/n-InP Schottky diode are 0.51 eV (I-V)/0.64 eV (C-V) and 1.81, respectively. When the contact is annealed at 200 o C in N2 atmosphere for 1min, a maximum SBH (0.71 eV (I-V)/0.81 eV (C-V)) and low ideality factor (1.15) are achieved for the Au/Cr/n-InP Schottky diode. However, after annealing at 300 o C, the SBH slightly decreases to 0.58 eV (I-V)/0.69 eV (CV), and ideality factor increases to 1.45, respectively. The SBHs obtained from the Norde and Cheung’s methods are closely matched with those obtained from the I-V method. Results show that the optimum annealing temperature for the Au/Cr/n-InP Schottky diode is 200 °C. Further, the discrepancy between SBHs calculated from I-V and C-V methods is also discussed. Moreover, the energy distribution of interface state density is estimated from forward bias I-V characteristics at different annealing temperatures. AES and XRD studies reveal that the formation of indium (In) phases at Au/Cr and InP interface may be the cause for the increase in SBH after annealing at 200 o C. The AFM results show that the overall surface morphology of Au/Cr Schottky contacts is considerably smooth at elevated temperatures. Indexing terms/

ISSN 2347-3487 824|P a g e S e p t e m b e r 1 3 , 2 0 1 4

1.INTRODUCTION
III-V compound semiconductor, especially indium phospide (InP) has received much attention for the fabrication of optoelectronics, microwave devices, integrated circuits used in modern high-speed optical communications and Schottky junctions etc. [1][2][3][4][5]. This is due to direct energy band gap, high electron mobility, radiation hardness and high saturation drift velocity. The Schottky diode is a fundamental component in solid state electronics and has received extensive attention over the few decades. The performance and reliability of Schottky barrier diodes (SBD) strongly depend on the MS interface. Hence it is important to have a full understanding of the reactions of metal contacts with InP. Therefore, the fabrication of high-quality, more reliable Schottky contacts to InP with high barrier height, low-leakage current and good thermal stability is still a challenge. Generally InP Schottky diodes show low barrier height (BH) than desirable due to many reasons. One of them may be the out diffusion of InP atoms into the deposited metal films leaving vacancies or defects within the band gap pinning the Fermi level [6].
Various metal schemes have been used for the formation of Schottky rectifiers on n-InP by many research groups. For example, Cetin et al. [7] prepared Au and Cr/n-InP Schottky barrier diodes and reported that the effective barrier height of the Au and Cr contacts were 0.480 eV, 0.404 eV and 0.524 eV, 0.453 eV from current-voltage (I-V) and capacitancevoltage (C-V) measurements, respectively. Huang et al. [8] studied a high performance of bilayer Pt/Al contacts on n-InP and found to be the effective barrier height of 0.74 eV and ideality factor of 1.11. Reddy et al. [9] investigated the electrical, structural and morphological characterstics of rapidly annealed Pt/Ti double metal structure on n-InP and reported that increase or decrease in Schottky barrier height upon annealing at elevated temperatures could be attributed to the formation of interfacial phases at Pt/Ti interface according to AES and XRD results. Devi et al. [10] investigated the electrical and structural properties of Au/Cu Schottky contacts on n-InP as a function of annealing temperature. They reported that the barrier height increased (0.82 eV (I-V) and 1.04 eV (C-V)) after annealing at 400 o C and decreased (0.75 eV (I-V), 0.88 eV (C-V) upon annealing at 600 o C. Huang and Horng [11] studied the electrical and structural properties of Pt/Al/n-InP Schottky diodes and reported that the double metal contact structure provides better rectification characteristics than single metal/n-InP Schottky diodes. Reddy et al. [12] investigated the annealing effect on electrical properties and interfacial reactions of Ni/Cu Schottky rectifiers on n-InP. They found that the barrier height decreased with annealing temperature compared to the as-deposited one. Bhaskar Reddy et al. [13] prepared the Au/Ni/n-InP Schottky barrier diode and reported that the barrier heights were effectively influenced by rapid thermal annealing. Naik et al. [14] investgated the electrical and structural properties of Pd/V/n-InP Schottky structure as a function of annealing temperature. They reported that the increase in barrier height after annealing at 200 o C might be due to the formation of indium (In) phases at interface vicinity. Recently, Yatskiv et al. [15] prepared Pt/InP Schottky contact by electrophoretic deposition of Pt nano particles and studied its electrical properties at different temperatures.
Our main objective of this work is to fabricate and characterize the Au/Cr Schottky contacts on n-InP as a function of annealing temperature. As far as we know, no one has investigated the electrical, structural and surface morphological properties of Au/Cr/n-InP Schottky contact at different annealing temperatures. In the present work chromium (Cr) is selected as the first layer since it has low work function as well as to provide the low forward voltage drop. Gold (Au) is used as the second layer in order to prevent oxidation as well as to promote current spreading in the contact and good smoothness to the contact. In this work, we investigate the electrical, structural and morphological properties of Au/Cr Schottky contact on n-type InP at different annealing temperatures. Using various analysis techniques (Forward I-V, C-V, Cheung and Norde methods), the diode parameters such as barrier height (Фb), ideality factor (n), series resistance (Rs), and interface state density (Nss) are calculated and discussed. Also, the interface analysis of Au/Cr/n-InP Schottky diode is investigated by auger electron spectroscopy (AES) depth profile and X-ray diffraction (XRD) measurements at different annealing temperatures.

2.EXPERIMENTAL DETAILS
Liquid Encapsulated Czochralski (LEC) grown undoped n-InP (100) samples with carrier concentration of 5×10 15 cm -3 were used in the present work. The wafers were initially degreased with organic solutions like trichloroethylene, acetone and methanol by means of ultrasonic agitation for 5 min in each stage to remove the contaminants followed by rinsing in deionised water and then dried in N2 flow. Further, the samples were etched with HF (49%) and H2O (1:10) to remove the native oxides from the wafer surface. Finally, the wafers were rinsed in deionised water. Ohmic contact on back side of the InP wafer was formed by deposition indium (In) metal (500Å) followed by rapid thermal annealing at 350 o C in N2 atmosphere for 1min. The metals Au/Cr (300/200 Å) layers were deposited on the polished side of the InP wafer with a diameter 0.7mm through a stainless-steel mask using a e-beam evaporation system. All evaporations process were carried out under a vacuum pressure of 5×10 -6 mbar. Sequentially, Schottky contacts were annealed at 100 o C, 200 o C and 300 o C under nitrogen ambient using a rapid thermal annealing (RTA) system. The current-voltage (I-V) and capacitancevoltage (C-V) characteristics of the Au/Cr Schottky contacts to n-InP were measured using a Keithley-source measuring unit (Model No 2400) and automated deep level spectrometer (SIMILAB DLS-83). To examine the intermixture of the Au/Cr metals with InP before and after annealing, auger electron spectroscopy (AES: UG: micro lab 350) depth profile was used. X-ray diffraction studies (Siefert XRD PW 3710) using Cu K radiation) were made to characterize the interfacial reaction between the InP and Au/Cr metal layers. Finally, atomic force microscopy (AFM) (Model No: a MOD-1M plus, Make: Nano focus; Operating mode: Non-contact, tip size <10 nm) was also employed to characterize the surface morphology of the Au/Cr Schottky contacts before and after annealing temperature. The forward and reverse bias I-V characteristics of Au/Cr/n-InP Schottky diodes are shown in Figure 1 as a function of annealing temperature. The leakage current of the as-deposited and annealed Au/Cr/n-InP Schottky diode at 100 o C are measured to be 9.961×10 -6 A and 8.001×10 -8 A at -1V. However, for the contact annealed at 200 o C, the leakage current slightly decreases to 5.373×10 -9 A at -1V. Further, with the increase in annealing temperature up to 300 o C, the leakage current increases to 8.079×10 -7 A at -1V compared to the annealed at 100 o C and 200 o C contacts. Experimental results indicate that the electrical properties of Au/Cr/n-InP Schottky diodes are improved after annealing at 200 o C. According to the thermionic emission (TE) theory, the current through a Schottky barrier diode (SBD) with the series resistance (RS) at a forward bias (V≥3kT/q) and is given by [

The Current-Voltage (I-V) Characteristics
where I is measured current, V is applied voltage, the term IRs is the voltage drop across the Rs of the diode, kB is the Boltzmann's constant, n is ideality factor, Io is reverse saturation current derived from the straight line of intercept of ln(I) at zero bias and it is given by where A is the effective area of Schottky contact, A* is the effective Richardson constant (the theoretical value of A * was 9.4 Acm -2 K -2 for n-InP [16] ), q is the charge of electron, T is the absolute temperature and Фb is the barrier height and is determined from the extrapolated Io and is given by

Figure 1.The reverse and forward (I-V) characteristics of the Cr/Au/n-InP Schottky diodes at different temperatures.
The experimental values of Schottky barrier height (SBH) of the as-deposited and 100 o C annealed contacts are found to be 0.51 eV and 0.63 eV respectively. However, the SBH increases to 0.71 eV for the contact annealed at 200 o C. Further, the SBH slightly decreases to 0.58 eV when the contact is annealed at 300 o C. These results indicate that the optimum annealing temperature for the Au/Cr/n-InP Schottky diodes is 200 o C. According to Duboz et al [17], the lower value of the barrier height for the sample annealed at higher temperature can be attributed to reduction in the density of interfacial defects. The modification of the defect density by annealing could change the pinning at the Fermi level resulting change in the barrier heights. The values of ideality factor n can be calculated from the slope of the linear region of the forward I-V characteristics for small forward bias currents where the series resistance is negligible. The ideality factor is given by 826|P a g e S e p t e m b e r 1 3 , 2 0 1 4 The ideality factor of as-deposited and annealed at 100 o C the Cr/Au/n-InP Schottky diodes are found to be 1.81 and 1.28 respectively. However, the ideality factor is improved to 1.15 for the contact annealed at 200 o C. Further, the ideality factor slightly increases to 1.45 for the contact annealed at 300 o C. It is noted that the ideality factor is greater than unity for all diodes. This non-ideal behavior can be attributed to (i) defect states in the band gap of the semiconductor providing other current transport mechanism such as barrier tunneling or generation, recombination in the space charge region [18], (ii) laterally inhomogeneous contacts [19] and (iii) interface dipoles caused by an interface and also fabrication induced defects at the interface. The deviation from linearity at higher voltage in the semi logarithmic I-V characteristics is due to the series resistance, the interface layer and interface states of the structures [20].
As it can be seen from Figure 1, at low forward bias voltages, the forward bias I-V characteristics are linear on a semi-logartimatic scale but deviate considerably from linearity which may be due to the effect of series resistances (Rs), the interface layer, and the interface states when the applied voltage is significantly large. The series resistance (Rs) is important in the downward curvature of the forward bias I-V characteristics, but the other two Schottky parameters such as barrier height Фb and ideality factor n are significant in both the linear and non-linear regions of the I-V characteristics. As the linear range of the forward I-V plots is reduced, the accuracy of the determination of SBH and ideality factor becomes smaller. Therefore Фb, n and Rs are also estimated from the downward curvature of the forward I-V plot, using Cheung's method [21]. Cheung's functions can be expressed as (6) and H(I) can also be written as  In order to determine the effective SBH and series resistance (Rs) of Au/Cr/n-InP Schottky diodes, the modified Norde function was also used [22]. In this method a function F(V) is plotted against the V (plot not shown here) and is given by where  is the integer (dimensionless) greater than ideality factor n and I(V) is the current obtained from the forward bias I-V curve. The effective SBH (Фb) is given by where F(Vmin) is the minimum point of F(V) and Vmin is the corresponding voltage. The value of series resistance (Rs) is also determined by the norde function and is given by The extracted SBH and series resistance (Rs) of the Au/Cr/n-InP Schottky diode are 0.53 eV, 320 Ω for as-deposited, 0.66 eV,199 kΩ for 100 C, 0.73 eV, 272 kΩ for 200 C, and 0.60 eV, 15 kΩ for 300 C respectively. It is observed that there is a good agreement among the values of Фb obtained from the forward bias I-V, Cheung's and Norde's methods. Also, series resistance (Rs) estimated by the Norde's method is comparable to that of the Cheung's method.
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Figure 3. plot of 1/C 2 versus V for the Cr/Au/n-InP Schottky diodes annealed at different temperatures
Capacitance-voltage (C-V) characteristics of the Au/Cr/n-InP Schottky diode are measured at 1MHz in the dark at room temperature. Figure 3 shows a plot of 1/C 2 as a function of bias voltage (V) for the as-deposited and annealed Au/Cr/n-InP Schottky diode. The relationship between the capacitance and the applied voltage in Schottky diodes is given by [1,23] where εs is the permittivity of the semiconductor (εs= 9.4 εo, where ε0 is the vacuum permittivity) of n-InP, Nd is the donor concentration, A is the area of the Schottky contact and Vbi is the flat band voltage respectively. The x-intercept of (1/C 2 ) versus V plot yields Vo and Vo is related to the built-in potential Vbi by the equation Vbi = Vo + kT/q, where T is the absolute temperature. The barrier height (Фb) is given by Фb= Vbi + Vn, where Vn = (kT/q) ln(Nc/Nd).The effective density of states in the conduction band edge is given by Nc = 2(2πm*kT/h 2 ) 3/2 , where m*= 0.078mo and its value is 5.7×10 17 cm -3 for InP [24] at room temperature. The SBH of as-deposited Au/Cr/n-InP Schottky diode is found to be 0.64 eV. The estimated SBHs are 0.75 eV for 100 °C, 0.81 eV for 200 °C and 0.69 eV for 300 °C annealed Au/Cr/n-InP Schottky diodes respectively. A summary of the basic electrical parameters of Au/Cr/n-InP Schottky diodes calculated from I-V and C-V characteristics at different annealing temperature is given in Table 1. As it can be seen from Table 1 that the barrier heights (Фb(I-V)) achieved from I-V measurements are significantly lower than those obtained from C-V measurements (Фb(C-V)). Various authors have reported the reasons for the difference in SBHs obtained from I-V and C-V measurements (in the literature) [25][26][27][28]. Based on Hacke et al. [25], the presence of a native oxide layer at the metal-semiconductor interface can cause the discrepancy between the measured Фb(I-V) and Фb(C-V). According to Song et al. [26] the inhomogeneity in the interface layer composition, non-uniformity of the interfacial layer thickness, and distribution of interface charges can also cause such differences in the SBH estimated from I-V and C-V measurements. Further, the surface damage at the metal-semiconductor interface affects the I-V measurements because defects may act as recombination centers for trap assisted tunneling currents according to Fontaine et al. [27]. One more possibility is that the product of reactions may not be uniform at the interface at a high annealing temperature. The type and reaction phases may vary from one location to another which cause different SBHs [28].
At high current region, there is always a deviation of the ideality factor which may be due to the presence of a interfacial layer between metal and semiconductor, interface states and series resistance. Thus, for estimating SBH and other characteristic parameters, the interface states play an important role in the semiconductor rectifying contacts. It is well known that for a metal/semiconductor diode having interface states in equilibrium with the semiconductor, the ideality factor n becomes greater than unity [29]. The expression of the density of interface states proposed by Card and Rhoderick is given by [29]   where εi =3.5εo and εs = 9.4εo are the permittivity of the interfacial layer and semiconductor, Nss is the interface state density, δ is the thickness of the interfacial layer and WD is the width of the space charge region. Further, in n-InP semiconductor the energy of interface states (Ess) with respect to the bottom of the conduction band at the surface of the semiconductor is given by [30,31,32].
where Ess is the energy corresponding to the bottom of the conduction band at the surface of the semiconductor and Фe is the effective barrier height, which depends on the applied bias due to an interfacial layer and is given by [33].
Thus, Eqs. (12)- (14), along with the I-V characteristics can be used for estimation of interface state density (Nss) as a function of interface state energy (Ess). The Nss versus Ec-Ess plot of the Au/Cr/n-InP Schottky diode is shown in Figure 4.

Figure 4. Density of interface states Nss as a function of Ec-Ess for the Cr/Au/n-InP Schottky diodes at various temperatures.
It can be seen from Figure 4, an experimental increase in interface state density exists from mid gap towards the bottom of the conduction band is very apparent, and Nss values obtained decreases with an increase of applied voltages. The value of interface state density is estimated for the as-deposited Au/Cr/n-InP Schottky diode is 2. potential drop across the interfacial layer varies with the bias. It alters the diffusion potential and therefore the depletion capacitance [1,24,33]. The expermental results show that the interface states density (Nss), and series resistance (Rs) has a significant effect on the electrical characteristics of the Schottky device.

Structural and Morphological Characteristics
AES depth profile measurement was employed to examine the variation in the BHs of the Au/Cr/n-inP Schottky diode before and after annealing at 300 o C in N2 ambient for 1 min. AES depth profiles of the as-deposited and annealed at 200 o C and 300 o C are shown in Figure 5. The atomic concentration percentage is recorded as a function of sputtering time to investigate the interfacial reaction between Au/Cr metal layers and InP film. The as-deposited layers Au/Cr, Figure 5(a), exhibit a relative sharp interface indicating that there is no significant inter-diffusion (or) out diffusion between the Au/Cr metal layers and InP layer. When the contact annealed at 200 o C, Figure 5(b) AES depth profile of the Au/Cr contact shows that indium (In) is out diffused into Au/Cr film this leads to the possibility of a reaction between Au/Cr and In film, resulting in the formation of Cr-In and Au-In interfacial phases during annealing at 200 o C at the interface vicinity. In Figure  5(c), a small change in the interface is observed with further out diffusion of In into Au/Cr layers. It is also noted that a small amount of phosphide (P) is out diffused into metal layers. This indicates the possibility of a P reaction with metal layers. These results lead to formation of phosphide (P) phases at interface during annealing at 300 o C as shown in Figure  5(c). Moreover, it is observed that a small amount of oxygen is observed in the interface for all contacts. This may be partially originated from the InP surface. Next, In order to understand the interfacial reactions between deposited metal layers and semiconductor, XRD measurements are performed before and after annealing temperature. Figure 6 shows the XRD spectra of Au/Cr/ n-InP Schottky diodes at different annealing temperatures. For the XRD spectra of the as-deposited contact, Figure 6 The atomic force microscopy (AFM) is also employed to characterize the surface morphology of the Au/Cr Schottky contacts before and after annealing at 300 o C in N2 ambient for 1min. Figure 7 shows the AFM images of the as-deposited Au/Cr Schottky contact and annealed at 200 o C and 300 o C. The scanned area of the sample is 5×5 µm 2 . The surface morphology of the as-deposited sample is fairly smooth with a root-mean-square (rms) roughness of 1.800 nm as shown in Figure 7(a). When contact is annealed at 200 o C, Figure 7(b), the surface morphology become somewhat degraded with an rms roughness of 3.075 nm. Further, increase in the annealing temperature up to 300 o C, Figure 7(c), it is observed that the surface morphology of the contact is slightly increased with an rms roughness of 7.307 nm as compared to the as- The experimental results exhibit that the barrier height (BH) increases for the contact annealed at 200 o C compared to asdeposited and 100 o C annealed contacts. However, the BH slightly decreases in annealing temperature upto 300 o C. The variation in the BH on annealing may be responsible for the formation of interfacial phases at the interface. The variation in BH of Au/Cr/n-InP Schottky diodes with annealing temperature can be explained based on the AES and XRD results. The XRD and AES depth profile results reveal that, as annealing temperature increases up to 200 o C, an interfacial region formed at the interface, with the out diffusion of indium (In) from the InP into Au/Cr layers as evident from AES and XRD measurements ( Figures.6 (b), 5 (b)). As a result, the formation of interfacial phases such as Au3In (110) (001), Au9In4 (211), Au7In3 (220), CrIn3 (111), In4Au9 (321) are responsible for the increase of the BH. The formation of these interfacial phases result in accumulation of fixed negative charge due to the presence of filled acceptors or electrons traps at the InP interface. The increase in the BH is always accompanied by a corresponding decrease in the reverse leakage current. However, the decrease in SBH upon annealing at 300 o C could be attributed the reaction of Cr layer with InP, resulting in the formation of phosphorous (P) phases at the interface vicinity (as evident from Figure 6(c)). The formation of phosphorous phases at interface may create phosphorus vacancies in InP which act as donors, as a result reducing the SBH at elevated temperature. In this case a positive charge state may exist at the interface due to loss of phosphorous from the surface which may reduce the SBH. These findings are consistent with the results which were previously reported by Andersson [34], Naik et al. [14]. The discrepancy of the BHs of Au/Cr Schottky contacts is mostly due to the observed structural changes of the Au/Cr contacts at the interface.

4.CONCLUSIONS
The electrical, and structural properties of Au/Cr/n-InP Schottky diode have been investigated by I-V, C-V, AES and XRD measurements at different annealing temperatures. The estimated Schottky barrier height (SBH) and ideality factor (n) of the as-deposited Au/Cr/n-InP Schottky diode are 0.51 eV (I-V)/0.64 eV (C-V) and 1.81, respectively. When the contact is annealed at 200 o C in N2 ambient for 1 min, a maximum SBH and low ideality factor are achieved for Au/Cr/n-InP Schottky diode and the corresponding values are 0.71 eV (I-V)/0.81 eV (C-V) and 1.15. However, the SBH slightly decreases to 0.58 eV (I-V)/0.69 eV (C-V), and ideality factor increases to 1.45 upon annealing at 300 o C. Further, it is noted that the SBHs extracted from the C-V measurements are higher than that obtained from I-V measurements. The SBHs obtained from the Norde and Cheung's methods are closely matched with those obtained from the I-V method. Results show that the optimum annealing temperature for the Au/Cr/n-InP Schottky diode is 200 °C. It is noted that the extracted interface state density Nss decreases with an increase in annealing up to 200 o C and then slightly increases upon annealing at 300 o C. Based on the AES and XRD results, the formation of indium phases at the interface may be the reason for the increase of SBHs after annealing at 200C. The decrease in SBH for contact annealed at 300C may be the reason for the formation of phosphide phases at the interface. The AFM results show that the surface morphology of the as-deposited Au/Cr Schottky contacts (rms roughness of 1.800 nm) is increased for the contact annealed at 300 o C (rms roughness of 7.307 nm). Expermental results indicate that the Au/Cr Schottky contact may be good choice for the development of InPbased electronic device applications.